1. Field
The following description relates to a technique for detecting false sharing.
2. Description of the Related Art
A symmetric multiprocessor (SMP) includes multiple CPUs or cores each having a local cache guaranteeing cache coherence of the local cache. False sharing is a phenomenon in which an identical data block is cached when threads performed on different CPUs access different memory addresses.
In addition, when a cache line loaded due to false sharing is updated by a thread of one CPU, a memory system of the SMP guaranteeing the cache coherence invalidates a cache line of another CPU which caches the same data block in cooperation with the one CPU. Accordingly, when a thread of the other CPU accesses the cache line of the other CPU again, a data block needs to be reloaded and newly cached and thus the system performance is degraded from the reloading of the data block.
Such false sharing needs to be avoided when developing a multi-thread application designed to run in a multi-core environment. According to an example of a method for detecting false sharing, a performance counter may be used to measure CPU performance. However, this method does not detect potential false sharing before false sharing occurs but instead detects the occurrence of false sharing that has happened by detecting a change in performance resulting from the false sharing. However, in order to detect false sharing during the development stage of multi-thread applications, identification of a chance of false sharing needs to be detected in advance during the development stage.